1. Field of the Invention
This invention relates generally to integrated circuits (ICs) and more particularly concerns low power consuming scan cells that can be used to perform at-speed testing in scan mode testing with reduced heat dissipation.
2. Description of the Related Art
In an effort to remain competitive in the marketplace, chip manufacturers are constantly striving to optimize the design and efficiency of their ICs by increasing chip speed, quality and the density of internal circuit components. Commensurate with meeting these objectives is to maximize fault coverage when testing their IC designs. A common industry design practice is to make the IC design scannable by implementing scan cells. Among many types of scan cells, the most common one is the so called "muxed-scan," or also referred to herein as a "scan flop." FIG. 1A illustrates a conventional scan flop 100 having a multiplexer 102 and a D flip flop 104. Generally, the scan flop 100 has a system data input (DI) and a scan data input (SI) that are respectively connected to the multiplexer 102. The muliplexer 102 is configured to receive a scan enable (SE) and output a signal to a D input of the D flip-flop 104. The scan flop 100 also receives a clock signal (CP) which is communicated to the D flip-flop 104, and output pins Q and NQ that are also selectively output from the D flip-flop 104. The scan flop is therefore configured to operate in one of two modes. The first mode is a "system" mode (also known as the functional mode), and the second mode is a "scan" mode (also known as the test mode).
FIG. 1B illustrates a simplified semiconductor chip 101 having a scan chain that is made up of a plurality of interconnected scan flops 100. In actuality, when a full-scan design is implemented for a semiconductor chip 101, many more scan chains are integrated into the IC design to enable the scan test to achieve the highest fault coverage. However, for this simplified example, the first scan flop 100 of the scan chain has its scan data input (SI) connected to a pad 100, and a pad 112 connected to the output pin Q of the last scan flop 100. Also shown is a clock (CLK) pad connected to each of the clock signals (CP) of the individual scan flops 100. The output pins Q of each of the scan flops 100 of the scan chain are shown connected to the scan data inputs (SI). In this common scan chain design, non-scan chain logic 106 is also connected to the output pins Q and the scan data inputs (SI).
Additionally, non-scan chain logic 106 may further be connected to the output pins NQ. When the scan flop 100 is in the system mode, the scan enable (SE) signal is constrained to ground, such that the scan flop 100 operates identically to the D-flip-flop 104. In the scan mode, the scan enable (SE) signal is active high in shifting. In general, the test vector is scanned into each one of the scan flops 100 one clock at a time. Therefore, if a particular scan chain has 1000 scan flops 100, the scan chain would take 1000 clock shifting cycles to load. Unfortunately, for the test vector to be passed to and stored into each of the scan flops 100 of the scan chain, the non-scan chain logic 106 that is driven by the Q output pins and NQ output pins will necessarily be switched as well.
To illustrate this, table 1 provides two exemplary designs A and B. The illustrated non-shifting cycles are typically parallel measure cycles and parallel capture cycles, which are used to test the integrity of circuitry that is outside of the scan chain.
TABLE 1 ______________________________________ Shifting Non-Shifting Total Shifting Cycles Design Cycles Cycles Cycles vs. Total Cycles ______________________________________ A 704,225 3,821 708,343 99.46% B 319,734 1,171 320,905 99.64% ______________________________________
As illustrated in table 1, the shifting cycles are approximately 99% of the total clock cycles during scan testing. Because in scan testing all scan flops are toggling simultaneously, all logic driven by the scan flops 100 (e.g., the non-scan chain logic 106) is also simultaneously affected although it has nothing to do with shifting and fault detection. The switching activity in scan mode can therefore exceed that of system mode. Excessive switching, in CMOS integrated circuit designs is generally undesirable because power consumption and heat dissipation is directly proportional to switching activity. That is, the heavier the switching activity, the more power a design needs.
Although the heavier switching activity in scan mode has not received much attention in the semiconductor industry, the heavier switching activity does pose a substantial limitation during testing. This limitation is that scan mode testing can not be performed at the same clock speed as the device is designed to operate in its system mode. In a recent article describing the testing of the PowerPC 604e.TM. Microprocessor, the inherent limitation in scan mode testing was exemplified by the author's strong recommendation that testing be performed at frequencies of about 60 MHz. "Test Methodology for the 0.25 micron PowerPC 604e.TM. Microprocessor," Rajesh Raina et al., DesignCon98: On-Chip System Design Conference, pp. 427-444 (1998), this article is hereby incorporated by reference. Because the system mode operation of the PowerPC 604e.TM. Microprocessor is targeted to be between 250 MHz and 350 MHz, it should be readily apparent that such low frequency testing may not detect those faults that will only be discovered when the chip is operating in system mode (e.g., such as timing faults). Many times, such late discovery may result in failures that are only discovered by the end user.
In view of the foregoing, there is a need for scan cells that will enable "at speed" testing, while eliminating unnecessary switching of logic that is outside of a scan chain, which also reduces power consumption and heat dissipation. There is a further need for scan cells that achieve the foregoing, while maintaining the simplicity of standard scan flop cells.